The present invention relates to a register system of a microcomputer having a register including at least one register bit, and having an additional storage arrangement that is allocated to the register, and on which the data content of the register can be intermediately stored.
A microcomputer may include a plurality of different registers to increase the processing speed. Thus, for example, the microprocessor of a microcomputer may include a data register and an address register in its execution unit. For floating-point calculation, the processor may include a plurality of registers (arithmetic registers) in the floating point unit (FPU), and for calculation with whole numbers it may include a plurality of such registers in the integer unit (IU). In addition, a microprocessor may also include command registers.
Data is filed in the registers by applications that run on the microcomputer. If an application using a register is interrupted by a higher-priority application wishing to use the same register, the register must be freed for the higher-priority application as quickly as possible and without data loss. For this purpose, the data, filed in the register, of the lower-priority application may be stored intermediately in an additional storage arrangement. The additional storage arrangement may include, for example, a stack on which the data of the register are saved. The higher-priority application may then file its data in the register. After the termination of the higher-priority application, the data saved on the stack may be loaded back into the register, and the interrupted, lower-priority application may then be continued.
A plurality of applications having different priorities may be executed in nested fashion, so that the data of a plurality of interrupted applications are filed on the stack temporarily. For example, in microcomputers used for real-time processing, lower-priority applications may be interrupted by higher-priority applications, and the data of the lower-priority applications should be saved from the register on a stack. Interrupts are used for the interruption of the lower-priority application.
However, the saving of the content of a register on a stack may require a relatively large number of clock pulses of the CPU. After the interruption of a lower-priority application during the saving of the data content of the register on a stack, a delay may result before the register is free, and before the higher-priority application may be processed and may execute its actual tasks.
To reduce or avoid this delay of a higher-priority application, the additional storage arrangement may include register banks, i.e., to multiply realize the registers of the microcomputer. When necessary, the data from the register may be saved in a short time on the register banks, with a relatively small number of clock pulses. However, the register banks are complete registers. Since the flip-flops require a relatively large surface, the-register banks correspondingly require a large amount of silicon surface. However, for reasons of space and cost, a microprocessor should be implemented on a silicon surface that is as small as possible, or as many registers as possible should be situated on the same surface.
An object of an exemplary embodiment according to the present invention is to construct and develop a register system so that the computing time for saving data content of the register is reduced, while the silicon surface required for the register system is kept as small as possible.
To achieve this object, based on the register system of the type named above, an exemplary embodiment according to the present invention provides the additional storage arrangement as at least one shift register having at least two shift register cells, the content of an arbitrary shift register cell being transferable into a register bit, and, conversely, the content of a register bit being transferable into an arbitrary shift register cell.
In German Published Patent Application No. 196 11 520, an IDDQ test for a computer is referred to, in which a control unit contains an arrangement that causes the computer to assume particular operating states. In addition, an acquisition arrangement is provided that acquires the current or the voltage of the power supply circuit of the computer, whereupon, in a comparator arrangement, the acquired current or the acquired voltage is compared with at least one predetermined threshold value. For the actuation of the display device and/or of the switching off, an actuating arrangement is provided that, depending on the result of the comparison, displays an error if necessary, or, in reaction to such an error, causes the entire system or subareas of the system to switch off.
In an exemplary register system according to the present invention, the register is therefore not multiply realized, but rather is merely provided with at least one additional shift register for the saving of the data content of the register. Moreover, since shift registers require a smaller silicon surface than do register banks that are equivalent in terms of storage space, an exemplary register system according to the present invention may require a small silicon surface.
For the saving of the data content of the register in the shift register, a smaller number of clock pulses may be required, in which the content of the register is saved on a stack.
An exemplary register system according to the present invention therefore requires a low number of clock pulses of the CPU for the saving of the data content of the register, while requiring only a small silicon surface.
If static structures (CMOS architecture) are used exclusively in an exemplary register system according to the present invention, then the functional capacity of the microcomputer may be tested with the aid of an IDDQ test. The IDDQ test is based on the fact that error-free CMOS circuits have an extremely small power consumption when they are in an idle state. An error in the CMOS circuit may result in a significant increase in the power consumption. It is understood that the IDDQ test is described in detail on the website of the Center for Electronic Design, Communications and Computing.
According to an exemplary embodiment of the present invention, a shift register is allocated to each register bit of the register. In this manner, the content of an arbitrary register bit may be shifted into the shift register allocated to the register bit as needed. In this way, the saving of the data content of the register to the shift register may be simplified and accelerated.
According to another exemplary embodiment of the present invention, each shift register cell is a charge-coupled device (CCD) element. For example, each shift register cell may have a cell transfer gate, a charge storage unit, and an inverter. A shift register cell fashioned in this way does not constitute a complete flip-flop, and thus requires a correspondingly smaller amount of silicon surface. Nonetheless, the memory cells of the shift register according to an exemplary embodiment of the present invention may receive the content of a register bit rapidly and reliably, may store it intermediately at least for the duration of the loading of the register by a higher-priority application, and, after termination of the higher-priority application, may transfer it rapidly and reliably back into the register bit.
The inverter may include two transistors connected in series. The cell transfer gate includes at least one transistor. The charge storage unit of an exemplary shift register cell according to the present invention may be a gate capacitor of the inverter. Alternatively, the charge storage unit may be a separate capacitor. According to this exemplary embodiment, the shift register cell thus has only three transistors. In contrast, for example, it is believed that an SRAM storage cell has six or four transistors. It is also believed that a DRAM cell has only one transistor, but requires an extensive refresh logic unit.
According to another exemplary embodiment of the present invention, an input transfer gate is situated between the register and the first shift register cell. According to yet another exemplary embodiment of the present invention, the last shift register cell is connected with the first shift register cell via an output transfer gate. By opening the output transfer gate, the content of the last shift register cell may be shifted into the first shift register cell, as long as its transfer gate is open. If the transfer gate of the first shift register cell is closed and the input transfer gate is open, the content of the last shift register cell may also be shifted directly into the register bit to which the shift register is allocated.
The cell transfer gates are connected with a clock generator to shift the data contents of the shift register cells from one shift register cell to the next in the pulse of the clock generator. Likewise, the input transfer gate and the output transfer gate are connected with a clock generator. By controlling, i.e., opening or closing the various transfer gates of the shift register in the pulse of the clock generator, the data contents of the register may be received, shifted back and forth within the shift register, and transferred to the register again. The clock generator may be clocked by the system clock of the microcomputer or a multiple thereof.